Bullet Proofing The EFB Cathode Bias Regulator -- Including November 2025 Update

[Retrovert]

Additional data from National Semiconductor, the original source for the LM317 and friends:

https://www.ti.com/lit/ug/snoa826/snoa826.pdf?ts=1616616335945
LM317, LM340, LP2975: A User’s Guide To Compensating Low-Dropout Regulators
by Chester Simpson
National Semiconductor

The NPN Darlington pass transistor configuration requires that at least 1.5V to 2.5V be maintained from input-to-output for the device to stay in regulation. This minimum voltage “headroom” (called the dropout voltage) is given by:

VDROP = 2VBE + VSAT (NPN REG)​

...

Feedback is used in all voltage regulators to hold the output voltage constant. The output voltage is sampled through a resistive divider (Figure 5), and that signal is fed back to one input of the error amplifier. Since the other input of the error amplifier is tied to a reference voltage, the error amplifier will supply current as required to the pass transistor to keep the regulated output at the correct DC voltage.

It is important to note that for a stable loop, negative feedback must be used. Negative feedback (sometimes called degenerative feedback) is opposite in polarity to the source signal (see Figure 6).

Because it is opposite in polarity with the source, negative feedback will always cause a response by the loop which opposes any change at the output. This means that if the output voltage tries to rise (or fall), the loop will respond to force it back to the nominal value.

Positive feedback occurs when the feedback signal has the same polarity as the source signal. In this case, the loop responds in the same direction as any change which occurs at the output. This is clearly unstable, since it does not cancel out changes in output voltage, but amplifies them.

It should be obvious that no one would intentionally design positive feedback into the loop of a linear regulator, but negative feedback becomes positive feedback if it experiences a phase shift of 180°.

...

POLES

A pole (Figure 8) is defined as a point where the slope of the gain curve changes by -20 dB/decade (with reference to the slope of the curve prior to the pole). Note that the effect is additive: each additional pole will increase the negative slope by the factor “n” X (-20 dB/decade), where “n” is the number of additional poles.

The phase shift introduced by a single pole is frequency dependent, varying from 0 to -90° (with a phase shift of -45° at the pole frequency). The most important point is that nearly all of the phase shift added by a pole (or zero) occurs within the frequency range one decade above and one decade below the pole (or zero) frequency.

NOTE: a single pole can add only -90° of total phase shift, so at least two poles are needed to reach -180° (which is where instability can occur).

ZEROES

A zero (Figure 9) is defined as a point where the gain changes by +20 dB/ decade (with respect to the slope prior to the zero). As before, the change in slope is additive with additional zeroes.

The phase shift introduced by a zero varies from 0 to +90°, with a +45° shift occurring at the frequency of the zero.

The most important thing to observe about a zero is that it is an “anti-pole”, which is to say its effects on gain and phase are exactly the opposite of a pole.

This is why zeroes are intentionally added to the feedback loops of LDO regulators: they can cancel out the effect of one of the poles that would cause instability if left uncompensated.

...

The plot of Phase Shift shows how the various poles and zeroes contribute their effect on the feedback signal. To produce this plot, the phase shift at each frequency point was calculated based upon summing the contributions of every pole and zero at that frequency. The phase shift at any frequency “f” which is caused by a pole located at frequency “fp” can be calculated from:

Pole Phase Shift = - arctan (f / fp)​

The phase shift resulting from a zero located at frequency “fz” can be found using:

Zero Phase Shift = arctan (f / fz)​

Is this loop stable? To answer that question, we need only know the phase shift at 0 dB (which is 1 MHz in this case). Finding this does not require complex calculations:

As stated in the previous sections, a pole or zero contributes nearly its full phase shift in the frequency range one decade above and below the center frequency of the pole (or zero). Therefore, The first two poles and the first zero contribute their full phase shifts of -180° and +90°, respectively, resulting in a net phase shift of -90°.

The final pole is exactly one decade below the 0 dB frequency. Using the formula for Pole Phase Shift, this pole will contribute -84° of phase shift @ 1 MHz. Added to the -90° from the two previous poles and the zero, the total phase shift is -174° (which means the phase margin is 6°). This loop would either oscillate or ring severely.

...

To reduce the negative phase shift (and prevent oscillations), a zero must be added to the loop. A zero can contribute as much as +90° of positive phase shift, which will cancel out the effects of one of the two low frequency poles.

All monolithic LDO regulators require that this zero be added to the loop, and they derive it from a characteristic that is inherent in the output capacitor: equivalent series resistance (usually referred to as ESR).

...

The ESR of the output capacitor puts a zero in the loop gain which can be used to reduce excess negative phase shift. The frequency where the zero occurs is directly related to the value of the ESR and amount of output capacitance:

FZERO = 1 / (2π X COUT X ESR)​

Using the example in the previous section (Bode plot shown in Figure 12), we will assume that the value of COUT = 10 µF and the output capacitor ESR = 1Ω, which means a zero will occur at 16 kHz.

Figure 14 shows how this added zero will change the unstable plot into a stable one:

The bandwidth of the loop is increased so that the 0 dB crossover frequency moves from 30 kHz to 100 kHz.

The zero adds a total of +81° positive phase shift at 100 kHz (the 0 dB frequency). This will reduce the negative phase shift caused by the poles PL and P1. Since the pole PPWR is located at 500 kHz, it adds only -11° of phase shift at 100 kHz.

Summing all poles and zeroes, the total phase shift at 0 dB is now -110°. This corresponds to a phase margin of +70°, which is extremely stable.

This illustrates how an output capacitor with the correct value of ESR can generate a zero that stabilizes an LDO.

...
HIGH ESR

Using the example developed in the previous sections, we will change the conditions and assume the ESR of the 10 µF output capacitor is increased to 20Ω.This will decrease the frequency of the zero to 800 Hz (Figure 16). Reducing the frequency of the zero causes the loop bandwidth to increase, moving the 0dB crossover frequency from 100 kHz to 2 MHz.

This increased bandwidth means that the pole PPWR occurs at a gain value of +20 dB (compared to -10 dB in Figure 14).

Analyzing the plot (Figure 16) for phase margin, it can be assumed that the zero cancels out either P1 or PL. This means the loop has a two-pole response with the low frequency pole contributing -90° of phase shift and the high frequency pole PPWR contributing about -76° of phase shift.

Although this appears to leave a phase margin of 14° (which might be stable), bench test data shows that ESR values > 10Ω usually cause instability because of phase shifts contributed by other high-frequency poles which are not shown in this simplified model.

...

LOW ESR

An output capacitor with a very low ESR value can cause oscillations for a different reason.

Continuing the example developed in the previous section, we will now reduce the ESR of the 10 µF output capacitor to 50 mΩ, increasing the frequency of the zero to 320 kHz (Figure 17).

When the plot is analyzed for phase margin, no calculations are required to see that it is unstable.

The -90° phase shift from each of the two poles P1 and PL will produce a total phase shift of -180° at the 0 dB frequency.

For this system to be stable, a zero is needed that would provide positive phase shift before the 0 dB point. However, since the zero is at 320 kHz, it’s too far out to do any good (and is cancelled out by PPWR).

OUTPUT CAPACITOR SELECTION

Since the output capacitor is the user’s tool for compensating a monolithic LDO regulator, it must be selected very carefully. Most cases of oscillations in LDO applications are caused by the ESR of the output capacitor being too high or too low.

When selecting an output capacitor for an LDO, a solid Tantalum capacitor is always the best choice. Tests performed on an AVX 4.7 µF Tantalum showed an ESR of 1.3Ω @ 25°C, a value that is almost perfectly centered in the stable region (Figure 15).

Also very important, the ESR of the AVX capacitor varied less than 2:1 over the temperature range of -40°C to +125°C. Aluminum electrolytic capacitors are notorious for exhibiting an exponential increase in ESR at cold temperatures, and are not suitable for use as an LDO output capacitor.

It must be noted that large (≥ 1 µF) ceramic capacitors typically have very low ESR values (< 20 mΩ), and will cause most LDO regulators to oscillate if connected directly to the output. A ceramic capacitor can be used if some external resistance is added in series with it to increase the effective ESR. Large value ceramics also have a poor tempco (typically Z5U) which means the capacitance will drop in half as the temperature is increased or decreased to the operating limits.
​

 

[Retrovert]

1. Without the traditional cathode bypass cap in place, the regulator will definitely become unstable. Whether it manifests itself as oscillation (which it must be), I don't know -- I just remember that early on, with no cap in place, the regulator would not function properly. When the cap was connected, the regulator instantly straightened up.

Yes, but that cathode-resistor bypass capacitor is too large and too slow to stabilize the regulator.

I suspect the fix is to add a smaller capacitor ≈ 10 µF with a resistor to simulate ESR of 1 to 3 Ω. I would not worry about the TempCo for other capacitor technologies, and it is not clear that the tantalums are reliable enough (failure takes out bias) nor standardized enough for the inherent ESR to be the universal panacea.

2. If it were an oscillation related event, I would think there would have been a more uniform failure rate between SS rectifier and Slow Warming Vacuum Tube power supply installations. [...] I would think there would be a more even distribution of failures -- and frankly -- far more failures if it is failing due to oscillation -- or at the very least, various issues/claims of poor amplifier performance. To my knowledge, there have never been any -- only the rare comment that a regulator shorted, and that the bias then could not be adjusted. The time element then is already coming into play.

Some additional speculation. Not sure if I have convinced myself of this.

The race condition resulting in runaway destruction only occurs with certain types of signal transitions.

I'd hazard a guess that changing from the slow-moving, low-frequency (< 100 Hz) signals to high-frequency, fast-moving (> 10,000 Hz) transients, or the reverse. Because of the short time required for the change the regulator cannot rapidly enough transition with accuracy (c.f. slew rates in opamps), overshoots, and then rings/oscillates its way back to stability.

At low frequencies the cathode-resistor bypass capacitor can sufficiently sustain the voltage that the regulator's hunting with be minimal, and the ringing will be damped as it normally would, particularly since large currents flow through the tube and this could dissipate the ringing/oscillation.

But at high frequencies the impedance of an electrolytic capacitor is too high to sustain, the movement of charge out of the capacitor is too slow, the currents are too small to properly damp the ringing/oscillation, and a risk of damage occurs. (This is why I often argue for smaller bypass capacitors made from film. The frequencies are below self-resonance, unlike a motherboard or cellphone, that a tank will not be formed by the different ESL and C.)

Here's some more speculation. Consider the limit condition at startup, when B+ is not flowing at all the ringing/oscillation cannot be damped by current flowing through the tube into a load. So the regulator is trying to force the output to a stable state and cannot do it once it overshoots the voltage and overcharges the bias capacitor. Maybe it's an over-current situation as it desperately tries to drive the output low to discharge the capacitor.

I'd hazard guess that the diodes are shifting the output voltage just enough to turn off the regulator, thereby providing stability until the initiation of current flow through the tube.

I suspect that in the general case some amount of ringing/oscillation in the MHz region is likely present, but it tends to be damped out by the nature of the music which reduces the demand for current. Nobody ever looked for it, and it might be very difficult to detect.

I'll certainly admit to being ill-schooled in the realm of keeping SS devices stable (other than the well established normal and ordinary measures), but I'm not sure I was aware that oscillation could even destroy a 3T regulator.

It is a common and well known problem for regulators to blow up with the wrong type of output capacitor.

This information was in the printed databooks, much like FDA black-box warnings.

Please do not think I'm in any way dismissing the possibility of instability -- anything is possible. But I'll let time, and others more equipped on this topic tell the tale of these possibilities. I do know however that the issues presented are proven to be beyond the "what if" realm, and solidly into the arena of facts that are known to be happening. If oscillation is found, then resolving it can only make the concept even more bullet proof.

Oh, no, so not taking it that way.

I view this as an engineering design review.

Many hypotheses are thrown out and retracted. Analysis is made, corrected, discarded, and/or accepted. Arguments are made and retracted. Positions staked out, modified, repudiated, re-introduced, modified, and again thrown out. etc. etc. etc.

The outcome hopefully is a triumph of truth, justice, and the American way, or, more likely, at least the prevention of most failures. It's never personal. This is why engineers tend to keep airplanes from falling out of the sky, and why bad management routinely ensures the opposite outcome.

The circuit does not lie to us, it performs in accordance with its design. The key is to maintain an open mind, such that hypotheses are created, tested, and then either accepted or rejected.

 

[trobbins]

Dave, perhaps in hind-sight the two stress modes could have been partially alleviated if the original common cathode resistor (R42) had not been 'completely' removed, but rather swapped for a higher resistance. I'd anticipate that the 337 would still effectively operate as intended during normal conditions, even if some common cathode current was being shunted by another path, and at start-up that alternative resistance path would suppress the stress levels experienced for the two stress modes.

But the disadvantage may have then been fewer field faults and a harder time in eeking out fault information, and so less incentive to delve in to a more rigorous assessment of initial conditions as a likely reason for stresses.

 

[dcgillespie]

The stress modes are occurring either (1) before the output tubes warm up in designs with a SS power supply, or (2) after the output tubes have begun to warm but before the rectifier tube has warmed in designs with a tube based power supply.

The first problem is the most unique, and present because there is no current flow between the IN and OUT terminals of the regulator in that scenario. I'm not sure how retaining some value of the original cathode resistance does anything to address this issue, since this resistance would effectively be connected directly across the IN and OUT terminals of the regulator, where there was already no current flowing to begin with. During normal stabilized operation (after the output tubes have warmed), retaining some value of cathode resistance would certainly act to limit dissipation from the regulator by partially bypassing the current through it -- which can be an effective tool, and is one I've previously used in other 3T applications for just that purpose (most recently, my ARC mystery D115/V70 project). But even without such a resistor, current limiting from the regulator's internal protection circuits due to excessive dissipation has never entered the picture -- even with tests that intentionally used inadequate heat sinking to check for such triggering.

The 3X diode string resolves the first issue by temporarily providing a current path for the OUT terminal of the regulator before the output tubes have begun to warm - doing so by tapping into the SS supplied voltage applied to the ADJ terminal during this time. When the output tubes begin to conduct, the diodes then completely disengage to become invisible to the circuit.

The second problem is more straight forward in resolve -- although certainly unique in the source producing the reverse voltage potential. Retaining some cathode resistance would act to reduce the reverse voltage applied to the regulator in this scenario by a unique amount in each application, but a conventional single back-diode strapped across the ADJ and OUT terminals would be more definitive in the protection provided from one installation to the next.

Dave

 

[egellings]

Thanks for the heads up. I'll add the protection diodes to my Dynaco ST-35, which has been working just fine with the original Gillespie mod.

 

[trobbins]

For stress mode 1, the output terminal is effectively floating but with a 120uF to gnd, and George's first plot shows the output terminal is charged up to circa 7Vpk (I can't make out the timescale) via an internal path from the adjust terminal which rises to circa 14Vpk. My initial thought was that some external loading on the output terminal could modify the internal circuit operation in a good way, although in hindsight it looks like suppressing the voltage reached by the output terminal may exacerbate the stress by forcing a higher voltage differential between adjust and output terminals, as well as a higher level of internal current flow during that time.

When I next have a Williamson on the bench I will try the EFB out to see how much influence it has - in that amp I have seen the common cathode voltage reduce slightly before clipping (rather than the typical increase seen in other autobias PP circuits). Protection of the 337 in that amp was primarily about the 40V in-out limit, but this thread has allowed other stress scenarios to be appreciated.

 

[GordonW]

For stress mode 1, the output terminal is effectively floating but with a 120uF to gnd, and George's first plot shows the output terminal is charged up to circa 7Vpk (I can't make out the timescale) via an internal path from the adjust terminal which rises to circa 14Vpk. My initial thought was that some external loading on the output terminal could modify the internal circuit operation in a good way, although in hindsight it looks like suppressing the voltage reached by the output terminal may exacerbate the stress by forcing a higher voltage differential between adjust and output terminals, as well as a higher level of internal current flow during that time.

When I next have a Williamson on the bench I will try the EFB out to see how much influence it has - in that amp I have seen the common cathode voltage reduce slightly before clipping (rather than the typical increase seen in other autobias PP circuits). Protection of the 337 in that amp was primarily about the 40V in-out limit, but this thread has allowed other stress scenarios to be appreciated.

The drop in cathode voltage near clipping in a cathode-bias amp, is classic blocking distortion. The grids of the output tubes are starting to draw a bit of current- which drives the bias more negative, by temporarily charging the coupling caps- making the net current draw go down a bit. That is a bit outside the scope of EFB- it would take Class A2 or AB2 operation (somehow low-impedance-DC-coupling the output tube grids, in effect), to keep that from happening.

Regards,
Gordon.

 

[dcgillespie]

To finish out the installation of the protection diode package in other amplifiers where the EFB modification is often installed, I've included two pics showing the packages installed on popular EFB power supply boards for both of Dynaco's small amplifiers. If previously installed, the boards will need to be removed to install the diode package:

On the SCA-35 Board:


On the ST-35 Board:


Dave

 

[thorpej]

The datasheets from TI (nee National) and ON Semi still specify tantalum "for stability". I checked that to verify. I found some TI blog entries which discuss the same cure I mentioned, namely adding additional resistance to the lower-ESR capacitor.

Indeed, either that or they specify an acceptable ESR range. LM2940 data sheet is a good example:

<quote>

The output capacitor, COUT, must have a capacitance value of at least 22 μF with an ESR of at least 100 mΩ, but no more than 1 Ω.​

</quote>

 

[Retrovert]

Indeed, either that or they specify an acceptable ESR range. LM2940 data sheet is a good example:
<quote>

The output capacitor, COUT, must have a capacitance value of at least 22 μF with an ESR of at least 100 mΩ, but no more than 1 Ω.​

</quote>

Clearly considerably varies by the regulator. I note that regulator is from National, not the TI data I quoted. While National was absorbed by TI, the regulator would have been created by a different design team.

Considerable effort must have been expended to stabilize the regulator with such little ESR, at least compared to what TI requires. Tantalum capacitors typically have an ESR > 1 Ω. My expectation would be that for most regulators that 100 milliΩ is consequently pushing the envelope to unacceptable regions and that oscillation would surely result. From everything I've read, 1 Ω is the least that would be acceptable to ensure adequate losses and thereby damp the oscillations. I have not done the experiments to see where the regulator becomes unstable.

Again that National regulator may have different properties.

In #18 I quoted from TI which explained the "tunnel of death" (surely the coolest name for an electronics phenomenon) and gave the range for acceptable ESR (in part):

Technical Review of Low Dropout Voltage Regulator Operation and Performance
Application Report SLVA072
Texas Instruments
(1999, August)

Section 9: Range of Stable ESR (Tunnel of Death)
Page 18​

Since ESR can cause instability, LDO manufacturers typically provide a graph showing the stable range of ESR values. Figure 25 shows a typical range of ESR values with respect to the output currents. This curve is called tunnel of death. The curve shows that the ESR must be between 0.2 Ω and 9 Ω. Solid tantalum electrolytic, aluminum electrolytic, and multilayer ceramic capacitors are all suitable, provided they meet the ESR requirements.​

The fact that the lower range is merely twice that quoted for the LM2940 and the upper range is nine times the quoted suggestion, indicates that regulators have wildly different needs and it would behoove the builder to carefully investigate the minimum ESR required to ensure the regulator's stability is maintained inside the SOA.

 

[Sphinx105]

Dave, thanks for posting this modification. I too experienced the failure on my first implementation in a 9300 and thought I had fat fingered a connection. I'll add the diodes.

 

[r100tsl7]

Thanks, Dave for this great info. I plan on incorporating this bias into my amps. I have had a love-hate relationship with st35/sca35 startup voltage. It's a pain to find newer tubes that will handle the 430v plus startup surge. They seem to work at first, but eventually one of them red plates. I'd watched the startup sequence closely and verified that when it happens, one of the tubes has a very slight positive grid bias, which creeps up slowly. It starts upon power on. I'd already replaced everything before I finally realized it was the tubes. Most vintage tubes handle it, but most russian tubes don't, and I've even seen EV's red plate.

I eventually tried the 10-dollar slow startup board from ebay on a SCA35 I rebuilt. It's been operating in the amp for 6 weeks now and works great. I adjusted it to kick in just after the tubes have started conducting. This has opened my selection of output tubes I can use with these amps. I suspect it may also eliminate the failure problem with the lm337, as normal voltage becomes present at startup. The board uses a massive AC relay with a good old 555 timer delay. It's very simple. Hopefully it will last. My brother-in-law has the amp and runs the snot out of it, so far so good. The whole family loves the sound.
When I get the amp back, I'll be putting in this biasing.

 

[gadget73]

I'd watched the startup sequence closely and verified that when it happens, one of the tubes has a very slight positive grid bias, which creeps up slowly.

I wonder if the root of this is a grid resistor value issue. Maybe the Russian tubes just won't survive with as high a value as old production tubes will.

 

[BrassTeacher]

 

[spantou01]

I’m planning to “bullet proof” my Dynaco SCA35 and ST35 which used the nice, but original, un-updated EFB PC boards I acquired from @dcgillespie ’s store. I already accomplished the diode fix detailed in this thread, that Dave explained and illustrated so well in post#28.

Now I’m looking for the preferred method to install the 200 Ohm resistor (or 2x100) between the input and output of the LM237 regulator on these original EFB boards, to update them as mentioned on the new schematics in Dave’s store.

Could anyone point me to these instructions if they had been issued. If not had anyone hacked their PCB’s for this install and how have you done it.

 

[dcgillespie]

NOVEMBER 2025 UPDATE

The update material provided earlier in this thread was released nearly five years ago now, with the intervening time since then confirming that it did in fact resolve the targeted issue -- that being the unexplained failure of some LM237 devices that defied any explanation as to why -- with some examples taking even years before suddenly failing. The update "bullet proofed" the regulator against all normal and most atypical use conditions, making its failure at best no more likely than that of any other component in the design. However, with time and input from the field over the past 5 years, new data has become available that has allowed the EFB™ circuit to be refined even further. In an effort then to have the EFB™ cathode regulator design provide the best possible performance, new updates to address those opportunities and the attending circuit changes are presented here:

2025 Update #1: There have been increased inquires lately regarding the range provided by the bias control relative to the use of 6BQ5 family tubes that require an unusually high amount of grid bias voltage to achieve the target 27 mA quiescent current flow per tube. That is, the quiescent current level couldn't be adjusted low enough to achieve the targeted value. This invariably involved use of Russian manufactured tubes, which have shown themselves to be excellent performers, but also have shown -- often times -- to require more grid bias voltage than tubes of bogey specification require to achieve a given quiescent current flow. But some examples have even shown to actually require less bias voltage than the bogey specification indicates, meaning that good as they are, these tubes can be all over the map relative to their bias characteristics -- even when purchased as a matched pair or quad. In my investigation, I found that this range can vary as much as nearly 25%, which is a very wide tolerance spread indeed. While the original EFB cathode regulator design could handle this range easily enough, when the previous update was implemented, it slightly reduced the range of the bias control on the low end of its range enough that tubes requiring a high bias voltage that resided at the extremes of the characteristic range couldn't be properly biased. For tubes that were anywhere close to the bogey characteristic it was no problem, but for those well out, it was. It was also found however that there was also an additional element that could compound the limited range even more.

2025 Update #2: A few users with R02 boards reported an upward creep of the test point bias setting with ambient heating of the amplifier. When reported, this invariably came from those who used the top cover on their amplifiers. If the output tubes installed were of the type that required an unusually high bias voltage, then for some users, the reading would creep above the range of the bias control before stabilizing.

It became apparent then that besides the range of the bias control needing to be increased back to its original capability, the thermal stability of the previous update also needed to be investigated as well, since the original EFB release did not display a thermal characteristic -- and the resolve of these items also needed to be achieved while still maintaining the regulator protections afforded by the previous update.

Both of these opportunities have now been well achieved, and achieved without any revisions required to the existing R02 boards offered for the small Dynaco amplifiers, and achieved while still providing the regulator protections of the previous update. The changes made include the following: (component designations are for the SCA-35, with ST-35 components in parentheses)

1. R7 (R7) Becomes 150K @ 1 Watt

2. R8 & R9 (R8 & R9) Both become 220Ω @ 2 Watts

3. D3, D4, D5, D6 (D3, D4, D5, D6) all get removed from the board.

4. Install at the D6 (D3) location a 3.0 volt @ 0.5 watt Zener diode type BZX79-B3V0, 113 or its equivalent. This diode is readily available at both Mouser and Digikey parts houses.

The new Zener should be installed with its orientation matching the existing orientation symbol shown for the original D6 (D3) diodes on these boards (banded end connects to regulator ADJ terminal). There are no new components to be installed at the D3, D4, D5 (D4, D5, D6) diode locations, so these component locations remain empty.

These changes will provide the greater range of the bias control in the original EFB release, while at the same time, making the circuit much more stable with regards to ambient temperature changes -- and all while still retaining the protection benefits afforded from the previous upgrade. The Assembly and Installation manuals for the Dynaco EFB™ Power Supply Boards have been appropriately updated (a tip-o-the-hat to George Ronnenkamp at Audio Regenesis for that effort), and are now available for uploading.

Dave

 

[Sam Cogley]

Sometimes, my slow as hell approach to building things works out. I’ll order the parts to upgrade the power board in the SCA-35 I have yet to finish.

 

[quadtech]

Thanks, Dave.
Errata -
In the ST35-EFB-R02-Installation-11-25.pdf , the schematic on page 15 shows R9 as 220K

 

[dcgillespie]

Quad -- Thanks so much for the catch! Of course the value of R9 should in fact be 220Ω. The error on the schematic has been corrected, and the corrected manual will be uploaded soon. Thanks again for the catch.

Dave

 

[grindfix]

Dave, I have the following EFB implementation Knight KN735 amplifier, minus the per-channel bias adjustment pots. I also see cathode current creeping with heat. Would the same zener mode apply here? Replace the 4 diodes with your specified zener ( cathode banded end towards ADJ terminal)?
Thanks