1) Why are you looking for Idss and pinchoff voltage? You are not operating on either condition, according to the schematic,On Q2, Vgs=5.4-4.2=-1.2V. You are operating at normal operation. That's the reason I said it before why are you worrying about the Idss and pinchoff voltage.
2) I would look for a FET that is has Vgs=-1.2V at Id=0.4mA. This is from calculating the current through R10( 10K at the drain of Q2).
I attached your schematic with the calculated current in red. It is a simple exercise of V=IR using the voltage given at each point. Q2 and Q4 forms a common two gain stages with negative feedback through R14. The gain of this amp is approx R14/R8 +1 which is 8.2K/3.9K+1=3.1. The exact bias is not that important. The exact voltage is not that important. I only point it's important is the voltage at the drain of Q2 or the base of Q4. You don't want to be over 22.5V. This has to do with the range of output swing. If the voltage is too high, the signal will clip on the positive swing.
View attachment 891821
Is this the real circuit you are using and to replace Q2? Or this is another exercise? If this is an exercise, this is a bad design. All the bias points relies on the Vgs of the transistor Q2. If Vgs change, it will upset the whole balance, it will change every single voltage. This is a single ended amplifier, distortion is going to be high. I use this circuit in a RF design where distortion is not important and is a very simple and cheap way to get a feedback amplifier of quite high frequency. Current through Q2 is very low, I would use at least 1 to 3mA. I would set the voltage at the drain of Q2 at about 16V to get maximum swing to avoid clipping and lower distortion because distortion rises as you swing close to the limit ( in your case is towards 25.5V)
You want to match the circuit, the most important thing is to match the voltages, which has a lot to do with the Vgs, NOT the Idss and pinchoff voltage.