We were discussing how long it would keep bias voltage off during power up. I was figuring charge time, not resonant frequency. Since it was a cap that was going from not charged; to charged on the turn on, I was calculating the simple time constant of 15,000x.00000047=.00705 seconds 1/.0075=141.8 , not the AC frequency of the RC circuit.
So the time it would take to charge is slightly less than .0083 seconds or 1/120 of a second half AC charge cycle. And yes, we could get technical and say that it is only charged to 62.3% of the final voltage, but I was trying to keep things easy to understand.
The point is that the assessment that this a power supply charge up circuit seems to make little sense. Why would delaying the full turn on of the output stage for a few ms be anything that would matter? How fast is the charge up time on the supplies, for example? Significantly less than 7ms?
Your reasoning seems to be a bit of a stretch. As someone who has actually designed these types of circuit and has used this very approach to do exactly what I have described with vbe multipliers, I would suggest that an alternative idea makes more sense...
Oh, and by the way it's not "resonant frequency", for that you'd need an LC or a negative resistance element or something besides just an R and a C.. it's effectively a "low pass cutoff frequency" although there is in fact a pole and zero involved in the transfer function. Yes, something in this will be resonant at some point, but this is not that.
Think of the operation this way. The resistor string between the collector of the bias transistor and the bottom of the diode (2vbe in total) consists of a 15k at the top and a c. 15k at the bottom (consisting of two resistors- one fixed, one variable) with the center connected to the base of the bias BJT. This provides roughly a 4vbe voltage across the bias string as it has a voltage gain of c.2. Just as you want.
After all, if you have 2vbe across the bottom resistor you must also have 2vbe across the top resistor (assuming zero base current for the BJT) giving a gain of 2.
The signal current is delivered through the collector of the transistor below and is applied into the load resistor above. Any change in the current- such as when a signal is amplified, results in a change in the vbe of the bias devices, this in turn is amplified by the bias circuit gain.
However, you don't want the operational AC voltage to be different at either side of the bias string as that changes the transfer function for one half versus the other, which is exactly what you do not want in an output stage as that causes crossover distortion, which is what you are trying to eliminate, so you want the bias string to be unity gain not x2 gain within the bandwidth of the amplifier. Hence the cap. It changes the gain at HF by shorting out the resistor to ac signals, and making the bias stage have unity gain. As a result the top and bottom of the bias network have the same ac potential. (note: well, not actually- the top would track the IR drop of the top load resistor, the bottom would experience a small extra delta V- but that's OK. If the stage was a x2 the top half would experience the expected drop minus this same delta V, and the bottom it plus a delta v- which is not good).
This ensures that both complementary halves of the output stage see the same driving AC potential but with the desired DC shift needed for the correct biasing of the output devices into the proper class AB region.
This is an alternative to sticking a cap right across the bias circuit, and in my opinion a good one as it avoids the actual resonance problems that can be caused due to the possible inductive behavior of the bias generator caused by the rise of "re" of the bias devices at very HF- which could cause a low loss LC parallel network to be formed at very HF. This could be a very bad thing to have.
You can add a damping resistor to take care of this, but why bother?
There may be other pathologies associated with that approach, ones that don't immediately spring to mind.
